Multistage counters of the type here envisaged are used, e.g. in communication system, to generate various timing signals recurring at predetermined intervals. In such a system, equipment handling incoming bit streams from several remote locations must extract different trains of clock pulses, ideally having the same cadence or repetition frequency, from respective message frames. The random phase relationship between the extracted clock-pulse trains, driving respective pulse counters of like counting capacity, can be detrimental to the operation of the system unless these counters are periodically realigned to correlate the timing signals emitted by them. Such correlation or realignment is also necessary where a plurality of identical but mutually independent pulse counters are isofrequentially stepped by respective clocks, for the sake of redundancy, to guard against malfunction of a timing unit including such a counter.
Conventional means for ascertaining a malfunction of a given timing unit include the provision in such unit of a primary and a secondary counting chain of identical construction driven by a common source of stepping pulses, the two chains working into respective inputs of a comparator designed to detect a possible disparity in their counts and to emit an alarm signal in the event of such disparity. During normal operation, the chains are periodically reset by respective control circuits, in response to full-count signals from their final stage outputs, for a simultaneous restarting of their counts.